Samsung patents chip design with uneven gate contacts for better manufacturing

1. A method of manufacturing a semiconductor device, comprising: preparing a substrate including a device region extending in a first direction and a field region extending in the first direction and spaced apart from the device region in a second direction intersecting the first direction; forming a base pattern extending in the first direction on the device region of the substrate; forming first and second dummy gate structures extending in the second direction on the substrate and spaced apart from each other in the first direction; forming a source/drain region recessing an upper surface of the base pattern exposed between the first and second dummy gate structures on the device region; forming a first interlayer insulating layer covering an upper surface of the field region of the substrate and an upper surface of the source/drain region; removing the first dummy gate structure to form a first gate space, and forming a first gate structure including a first gate electrode and a first gate capping layer on the first gate electrode in the first gate space; removing the second dummy gate structure to form a second gate space, and forming a second gate structure including a second gate electrode and a second gate capping layer on the second gate electrode in the second gate space; forming a source/drain contact plug penetrating the first interlayer insulating layer and contacting the upper surface of the source/drain region, wherein the source/drain contact plug includes a first portion and a second portion; forming a mask pattern overlapping the second portion of the source/drain contact plug in a vertical direction intersecting the first direction and the second direction; forming a source/drain contact pattern including the first portion and the second portion having different heights from each other by etching the first portion of the source/drain contact plug exposed from the mask pattern; planarizing until an upper surface of the second portion of the source/drain contact pattern is exposed; forming a first gate contact penetrating the first gate capping layer and contacting the first gate electrode, the first gate contact overlapping the device region in the vertical direction; and forming a second gate contact penetrating the second gate capping layer and contacting the second gate electrode, the second gate contact overlapping the field region in the vertical direction.