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Samsung patents chip design that tests circuits before cutting the wafer

Samsung describes a method for making semiconductor packages that includes specific test wires located in the gaps between individual chips. This setup allows engineers to run electrical checks on the circuitry before the wafer is physically cut into separate chips.

Why it mattersThis process helps ensure that only working chips are cut and packaged, which can reduce waste during manufacturing.

In the filing’s own words

A method for manufacturing a semiconductor package includes forming a semiconductor wafer including a substrate having main regions and a scribe region between the main regions, a wiring structure on the main regions, at least one test wiring structure on the scribe region, a low dielectric layer, an input/output pad on the wiring structure, at least one test pad on the at least one test wiring structure, and a first insulating layer,, performing an electrical test through the at least one test pad, forming a second insulating layer on the first insulating layer, forming a connection pad in the second opening, forming a recess extending from an upper surface of the second insulating layer toward the partial region,, and dicing the semiconductor wafer along a dividing lane.

What exactly they claim (claim 1)

1. A method for manufacturing a semiconductor package comprising: forming a semiconductor wafer comprising: a substrate having main regions and a scribe region between the main regions, a wiring structure on the main regions, at least one test wiring structure on the scribe region, a low dielectric layer surrounding a lower portion of the wiring structure and a lower portion of the at least one test wiring structure, an input/output pad on the wiring structure, at least one test pad on the at least one test wiring structure, and a first insulating layer surrounding an upper portion of the wiring structure, an upper portion of the at least one test wiring structure and covering the input/output pad and the at least one test pad, wherein the first insulating layer has at least one first opening on the at least one test pad and a partial region separating the low dielectric layer within the scribe region; performing an electrical test through the at least one test pad; forming a second insulating layer on the first insulating layer, the second insulating layer having a second opening on the input/output pad; forming a connection pad in the second opening; forming a recess extending from an upper surface of the second insulating layer toward the partial region, the recess having a lateral wall provided by the first insulating layer and the second insulating layer, and a bottom provided by the first insulating layer; and dicing the semiconductor wafer along a dividing lane, the dividing lane passing through the bottom of the recess, the partial region of the first insulating layer, and the substrate.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE
Publication number
US20260293615A1
Application number
19680905
Filed
May 18, 2026
Published
Sep 24, 2026
Inventors
4
Claims
20

Classified under

H10P 74/273 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 72/923 Electricity & electronicsH10W 72/934 Electricity & electronicsH10W 90/792 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.