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Samsung patents chip layout method using filler cells to adjust pattern density

Samsung describes a method for designing integrated circuits by placing standard logic blocks and adding specific filler cells. These filler cells are chosen from a library to adjust the density of metal patterns on the chip, which helps ensure the manufacturing process works correctly.

Why it mattersThis is a routine improvement in chip design software that helps manufacturers produce more reliable silicon by managing the physical layout of tiny metal connections.

In the filing’s own words

A method of fabricating an integrated circuit may include: arranging standard cells by referring to a standard cell library that includes information about a standard cell, and routing the standard cells that are arranged; arranging a filler cell of a selected type from among a plurality of filler cells to adjust a density of a pattern formed on at least one of the standard cells; and generating layout data based on the standard cells, including the filler cell, that are arranged. The standard cell library may include data defining the plurality of filler cells, and the plurality of filler cells may include a first filler cell and a second filler cell that each include at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern.

What exactly they claim (claim 1)

1. A method of fabricating an integrated circuit, the method comprising: arranging standard cells by referring to a standard cell library that includes information about a standard cell, and routing the standard cells that are arranged; arranging a filler cell of a selected type from among a plurality of filler cells to adjust a density of a pattern formed on at least one of the standard cells; and generating layout data based on the standard cells, including the filler cell, that are arranged, wherein the standard cell library comprises data defining the plurality of filler cells, wherein the plurality of filler cells comprise a first filler cell and a second filler cell that each comprise at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern, and wherein a density of one of the at least one pattern of the first filler cell is different from a density of one of the at least one pattern of the second filler cell.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
INTEGRATED CIRCUIT INCLUDING STANDARD CELL AND METHOD OF FABRICATING THE SAME
Publication number
US20260293319A1
Application number
19689594
Filed
May 27, 2026
Published
Sep 24, 2026
Inventors
6
Claims
20

Classified under

H10D 89/10 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 84/0149 Electricity & electronicsH10D 84/0186 Electricity & electronicsH10D 84/038 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.