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Samsung patents chip design with taller barriers between transistor channels

Samsung describes a semiconductor structure where two groups of transistor channels are separated by a physical barrier that is taller than the channels themselves. A gate electrode, which controls the flow of electricity, is placed over the channels and touches this taller barrier. This arrangement helps isolate the different parts of the chip from each other.

Why it mattersThis is a routine improvement in chip manufacturing that helps make transistors more reliable by better separating their components.

In the filing’s own words

An example semiconductor device comprises an active pattern on a substrate, a first channel structure and a second channel structure spaced apart from each other on the active pattern, a gate electrode on the first channel structure and the second channel structure and a separation structure provided between the first channel structure and the second channel structure. Each of the first channel structure and the second channel structure includes a plurality of semiconductor patterns. A level of an upper surface of the separation structure is higher than that of an upper surface of an uppermost semiconductor pattern among the plurality of semiconductor patterns. The gate electrode provided between the plurality of semiconductor patterns is in contact with the separation structure.

What exactly they claim (claim 1)

1. A semiconductor device comprising: an active pattern on a substrate; a first channel structure and a second channel structure spaced apart from each other on the active pattern; a gate electrode on the first channel structure and the second channel structure; and a separation structure between the first channel structure and the second channel structure, wherein the first channel structure includes a first plurality of semiconductor patterns and the second channel structure includes a second plurality of semiconductor patterns, wherein an upper surface of the separation structure is higher than an upper surface of an uppermost semiconductor pattern among the first plurality of semiconductor patterns and the second plurality of semiconductor patterns, and wherein the gate electrode contacts the separation structure.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Publication number
US20260293304A1
Application number
19327099
Filed
Sep 12, 2025
Published
Sep 24, 2026
Inventors
3
Claims
20

Classified under

H10D 84/852 Electricity & electronicsH10D 84/0167 Electricity & electronicsH10D 84/017 Electricity & electronicsH10D 84/0188 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.