Samsung patents new method for building semiconductor gate structures
Samsung has filed a patent application describing a specific method for manufacturing semiconductor devices. The process involves creating a trench in the chip's active area and filling it with alternating layers of insulating and conductive materials to form a gate structure. The filing details how the top of the first conductive layer is positioned lower than the surrounding insulating layer during the build.
In the filing’s own words
A method for manufacturing a semiconductor device includes providing a substrate, forming an active pattern disposed on the substrate and extending in a first direction, and a gate spacer extending in a second direction different from the first direction and defining a gate trench on the active pattern, forming a first gate insulating layer disposed along a sidewall and a bottom surface of the gate trench, forming a first conductive layer disposed on the first gate insulating layer inside the gate trench, forming a second gate insulating layer disposed on the first conductive layer inside the gate trench, and including a material different from a material of the first gate insulating layer, forming a second conductive layer disposed on the second gate insulating layer inside the gate trench, and forming a third conductive layer filling a remaining inner space of the gate trench on the second conductive layer.
What exactly they claim (claim 1)
1. A method for manufacturing a semiconductor device, the method comprising: providing a substrate; forming an active pattern disposed on the substrate and extending in a first horizontal direction, and a gate spacer extending in a second horizontal direction different from the first horizontal direction and defining a gate trench on the active pattern; forming a first gate insulating layer disposed along a sidewall and a bottom surface of the gate trench; forming a first conductive layer disposed on the first gate insulating layer inside the gate trench; forming a second gate insulating layer disposed on the first conductive layer inside the gate trench and including a material different from a material of the first gate insulating layer; forming a second conductive layer disposed on the second gate insulating layer inside the gate trench; and forming a third conductive layer filling a remaining inner space of the gate trench on the second conductive layer; wherein an uppermost surface of the first conductive layer is formed to be lower than an uppermost surface of the first gate insulating layer.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260293302A1
- Application number
- 19693459
- Filed
- May 31, 2026
- Published
- Sep 24, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 84/85 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6739 Electricity & electronicsH10D 62/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.