Samsung patents chip layout using two types of insulation layers
Samsung describes a method for building semiconductor chips by creating gaps between gate structures and filling them with specific insulating materials. The process uses silicon oxide for primary separation and silicon nitride for secondary isolation to manage electrical connections.
In the filing’s own words
A method of manufacturing a semiconductor device includes forming active regions on a substrate, forming a plurality of sacrificial gate structures intersecting the active regions on the substrate, forming source/drain regions on the active regions, removing the plurality of sacrificial gate to form gap regions, forming a plurality of gate structures in the gap regions, forming a first opening penetrating through the plurality of gate structures, forming a first isolation structure in the first opening to isolate the plurality of gate structures from each other, forming second openings penetrating through the first isolation structure, forming second isolation structures in the second openings, and forming a common contact plug disposed between the plurality of gate structures. The first isolation structure includes silicon oxide, and the second isolation structures include silicon nitride.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, comprising: forming active regions on a substrate, the active regions extending in a first direction and spaced apart from each other in a second direction; forming a plurality of sacrificial gate structures extending in the second direction and intersecting the active regions on the substrate; on the active regions, forming source/drain regions on at least one side of the plurality of sacrificial gate structures; removing the plurality of sacrificial gate to form gap regions; forming a plurality of gate structures in the gap regions, each of the plurality of gate structures extending in the second direction and intersecting the active regions on the substrate; forming a first opening penetrating through the plurality of gate structures and extending in the first direction; forming a first isolation structure in the first opening to isolate the plurality of gate structures from each other in the second direction; forming second openings penetrating through the first isolation structure and spaced apart from each other in the first direction; forming second isolation structures in the second openings; and forming a common contact plug extending in the second direction and disposed between the plurality of gate structures, wherein the first isolation structure includes silicon oxide, and the second isolation structures include silicon nitride.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING ISOLATION STRUCTURES
- Publication number
- US20260293301A1
- Application number
- 19683316
- Filed
- May 20, 2026
- Published
- Sep 24, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 84/85 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6729 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.