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Samsung patents chip design with stacked nanosheets and backside wiring

Samsung describes an integrated circuit design that stacks multiple thin sheets of silicon, known as nanosheets, to create the core of a transistor. The filing details a specific layout where electrical connections are routed from the back of the chip, using separation walls to keep these connections organized and distinct.

Why it mattersThis design aims to improve how electrical signals move through a chip by using a backside approach, which is a common strategy for making processors smaller and more efficient.

In the filing’s own words

An integrated circuit device includes an upper sheet separation wall, a pair of nanosheet stack structures having the upper sheet separation wall therebetween, disposed spaced apart from each other, and each comprising a plurality of nanosheets, a pair of gate electrodes on the pair of nanosheet stack structures, source/drain regions connected to ends of the plurality of nanosheets included in the pair of nanosheet stack structures, a pair of backside via contacts and connected to the pair of source/drain regions, a pair of backside wiring lines connected to ends of the pair of backside via contacts, and a lower sheet separation wall between the pair of backside via contacts and the pair of backside wiring lines, and contacting the upper sheet separation wall.

What exactly they claim (claim 1)

1. An integrated circuit device comprising: an upper sheet separation wall extending in a first horizontal direction and a vertical direction; a pair of nanosheet stack structures having the upper sheet separation wall therebetween, wherein a first nanosheet stack structure of the pair of nanosheet stack structures is spaced apart from a second nanosheet stack structure of the pair of nanosheet stack structures in a second horizontal direction that is different from the first horizontal direction, and each of the first nanosheet stack structure and the second nanosheet stack structure comprises a plurality of nanosheets; a pair of gate electrodes extending in the second horizontal direction on the pair of nanosheet stack structures; a plurality of source/drain regions connected to ends of the plurality of nanosheets included in the pair of nanosheet stack structures; a pair of backside via contacts adjacent to each other in the second horizontal direction and connected to a pair of source/drain regions of the plurality of source/drain regions; a pair of backside wiring lines connected to ends of the pair of backside via contacts; and a lower sheet separation wall between the pair of backside via contacts adjacent to the pair of backside wiring lines, the lower sheet separation wall extending in each of the first horizontal direction and the vertical direction, and contacting the upper sheet separation wall.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
INTEGRATED CIRCUIT DEVICE
Publication number
US20260293300A1
Application number
19447543
Filed
Jan 13, 2026
Published
Sep 24, 2026
Inventors
3
Claims
20

Classified under

H10D 84/833 Electricity & electronicsH10D 64/256 Electricity & electronicsH10W 10/17 Electricity & electronicsH10W 20/43 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 84/0153 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.