Samsung patents chip package with two different logic dies side-by-side
Samsung describes a semiconductor package that places two separate logic chips next to each other on a base structure. Each chip contains specific internal components like fin patterns and gate electrodes, allowing them to be electrically connected while remaining physically distinct.
In the filing’s own words
A semiconductor package includes a base structure, a first logic chip electrically connected to the base structure, and a second logic chip that is electrically connected to the base structure and that is spaced apart from the first logic chip in a first direction parallel to an upper surface of the base structure. The first logic chip includes a first fin pattern, a semiconductor pattern spaced apart from the first fin pattern, a first source/drain pattern connected to the semiconductor pattern, and a first gate electrode overlapping with the semiconductor pattern. The second logic chip includes a second fin pattern, a channel pattern connected to the second fin pattern, a second source/drain pattern connected to the channel pattern, and a second gate electrode overlapping with the channel pattern.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a base structure; a first logic chip electrically connected to the base structure; and a second logic chip that is electrically connected to the base structure and that is spaced apart from the first logic chip in a first direction parallel to an upper surface of the base structure, wherein the first logic chip comprises: a first fin pattern; a semiconductor pattern spaced apart from the first fin pattern; a first source/drain pattern connected to the semiconductor pattern; and a first gate electrode overlapping with the semiconductor pattern, and wherein the second logic chip comprises: a second fin pattern; a channel pattern connected to the second fin pattern; a second source/drain pattern connected to the channel pattern; and a second gate electrode overlapping with the channel pattern.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR PACKAGE
- Publication number
- US20260293299A1
- Application number
- 19360065
- Filed
- Oct 16, 2025
- Published
- Sep 24, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10D 84/832 Electricity & electronicsH10W 20/42 Electricity & electronicsH10W 74/131 Electricity & electronicsH10W 90/00 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.