Samsung patents chip design with lower power connections
Samsung describes a method for building a transistor where power connections are placed below the main contact points. The design uses a specific shape in the power connection to avoid overlapping with the transistor's base contact.
In the filing’s own words
An integrated circuit includes: a cell transistor including: a nanosheet stack including nanosheets spaced apart from each other in a vertical direction; a gate electrode on the nanosheet stack and extending in a horizontal direction; and a first source/drain region connected to the nanosheet stack; a back contact beneath the cell transistor and connected to the first source/drain region; a first power via at a vertical level lower than that of the back contact; a front wiring structure on and connected to the cell transistor; and a back wiring structure beneath the first power via and connected to the cell transistor. The back wiring structure is configured such that connected to the first power via and the back contact. And a lower surface of the first power via does not overlap the back contact in the vertical direction and includes a recess.
What exactly they claim (claim 1)
1. An integrated circuit device comprising: a cell transistor comprising: a nanosheet stack comprising a plurality of nanosheets spaced apart from each other in a vertical direction; a gate electrode on the nanosheet stack and extending in a horizontal direction; and a first source/drain region connected to the nanosheet stack; a back contact beneath the cell transistor and connected to the first source/drain region; a first power via at a vertical level lower than that of the back contact; a front wiring structure on and connected to the cell transistor; and a back wiring structure beneath the first power via and connected to the cell transistor, wherein the back wiring structure is connected to the first power via and the back contact, and wherein a lower surface of the first power via does not overlap the back contact in the vertical direction and comprises a recess.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- INTEGRATED CIRCUIT DEVICE INCLUDING A POWER VIA AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE
- Publication number
- US20260293296A1
- Application number
- 19392908
- Filed
- Nov 18, 2025
- Published
- Sep 24, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 84/8312 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/502 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 62/151 Electricity & electronicsH10D 64/256 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.