Samsung patents chip design with improved contact spaces
Samsung describes an integrated circuit design that uses a specific layout of vertical fins and isolation layers. The design creates a defined space between fin structures where electrical contacts can be placed to connect to the source and drain regions of the transistor.
In the filing’s own words
An integrated circuit device includes a fin-type active region including a first fin portion and a second fin portion apart from each other in a first lateral direction with a contact space therebetween, a first source/drain region on the fin-type active region at a position overlapping the contact space in a vertical direction, a gate line on the first fin portion, a device isolation film covering both sidewalls of each of the first and second fin portions and defining a width of the contact space, a back side source/drain contact electrically connected to the first source/drain region, filling the contact space, and having a sidewall facing each of the first and second fin portions and the device isolation film, and an etch stop layer contacting a top surface of each of the first and second fin portions between the first fin portion and the gate line.
What exactly they claim (claim 1)
1 - 20. (canceled)
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- INTEGRATED CIRCUIT DEVICE
- Publication number
- US20260293294A1
- Application number
- 19688020
- Filed
- May 26, 2026
- Published
- Sep 24, 2026
- Inventors
- 5
- Claims
- 21
Classified under
H10D 84/83 Electricity & electronicsH10D 84/0149 Electricity & electronicsH10D 84/038 Electricity & electronicsH10W 20/427 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.