Samsung patents stacked nanosheet design for next-gen chips
Samsung describes a semiconductor structure that stacks thin sheets of material vertically to create a transistor. A specific three-layer separation structure sits between the upper and lower sheets, using different materials to manage electrical flow.
In the filing’s own words
A semiconductor device includes an active pattern on a substrate, lower nanosheets disposed on the active pattern and spaced apart from each other in a vertical direction, a separation structure disposed on the lower nanosheets and including first to third layers stacked on each other, and upper nanosheets disposed on the separation structure and spaced apart from each other in the vertical direction. The lower and upper nanosheets form a multi-bridge channel field effect transistor. The second layer contacts the first and second layers. The first layer and the third layer include the same material. Each of the first layer and the third layer includes a material different from a material of the second layer. The second layer includes the same material as each lower nanosheet and each upper nanosheet.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate; an active pattern extending in a first horizontal direction on the substrate; a plurality of lower nanosheets stacked, while being spaced apart from each other in a vertical direction, on the active pattern; a separation structure spaced apart from the plurality of lower nanosheets in the vertical direction and disposed on the plurality of lower nanosheets, and including a first layer, a second layer, and a third layer that are sequentially stacked on each other; and a plurality of upper nanosheets spaced apart from the separation structure in the vertical direction and disposed on the separation structure, and stacked, while being spaced apart from each other in the vertical direction, on the separation structure, wherein the plurality of lower nanosheets and the plurality of upper nanosheets form a multi-bridge channel field effect transistor, wherein the second layer contacts each of the first layer and the third layer, wherein the first layer and the third layer include the same material, wherein each of the first layer and the third layer includes a material different from a material of the second layer, and wherein the second layer includes the same material as each lower nanosheet of the plurality of lower nanosheets and each upper nanosheet of the plurality of upper nanosheets.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260293233A1
- Application number
- 19685631
- Filed
- May 22, 2026
- Published
- Sep 24, 2026
- Inventors
- 3
- Claims
- 16
Classified under
H10D 62/115 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 64/017 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.