Samsung patents memory chip using tellurium and indium oxide transistors
Samsung describes a basic logic circuit called an inverter that uses two different types of oxide-based transistors. One transistor uses a tellurium oxide material to handle positive signals, while the other uses an indium oxide material to handle negative signals. These components are designed to be part of a memory device within an electronic apparatus.
In the filing’s own words
An inverter includes a first field-effect transistor including a first channel layer, a first source/drain electrode and a second source/drain electrode disposed on opposite sides of the first channel layer, a first gate electrode facing the first channel layer, and a first gate insulating layer between the first channel layer and the first gate electrode, and a second field-effect transistor including a second channel layer, a third source/drain electrode and a fourth source/drain electrode disposed on opposite sides of the second channel layer, a second gate electrode facing the second channel layer, and a second gate insulating layer between the second channel layer and the second gate electrode. The first channel layer includes a p-type oxide semiconductor based on tellurium oxide, and the second channel layer includes an n-type oxide semiconductor based on indium oxide.
What exactly they claim (claim 1)
1. An inverter comprising: a first field-effect transistor comprising a first channel layer, a first source/drain electrode and a second source/drain electrode spaced apart from each other on opposite sides of the first channel layer, a first gate electrode facing the first channel layer, and a first gate insulating layer between the first channel layer and the first gate electrode; and a second field-effect transistor comprising a second channel layer, a third source/drain electrode and a fourth source/drain electrode spaced apart from each other on opposite sides of the second channel layer, a second gate electrode facing the second channel layer, and a second gate insulating layer between the second channel layer and the second gate electrode, wherein the second source/drain electrode and the third source/drain electrode are electrically connected to each other, the first channel layer comprises a p-type oxide semiconductor based on tellurium oxide, and the second channel layer comprises an n-type oxide semiconductor based on indium oxide.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- INVERTER INCLUDING OXIDE SEMICONDUCTOR, MEMORY DEVICE INCLUDING INVERTER, AND ELECTRONIC APPARATUS INCLUDING MEMORY DEVICE
- Publication number
- US20260293213A1
- Application number
- 19559429
- Filed
- Mar 6, 2026
- Published
- Sep 24, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10D 30/6756 Electricity & electronicsH02M 7/5383 Electricity & electronicsH10B 10/125 Electricity & electronicsH10D 30/6731 Electricity & electronicsH10D 30/6732 Electricity & electronicsH10D 30/6736 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.