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Samsung patents stacked memory chips with built-in circuit layers

Samsung describes a design for 3D memory where multiple layers of memory cells are stacked vertically on a single base. Each layer includes its own control circuits and vertical wires that connect the different levels together.

Why it mattersThis layout helps manufacturers pack more data into a smaller space, which is a standard approach for making faster and denser computer memory.

In the filing’s own words

A semiconductor memory device according to some implementations of the present disclosure includes a memory cell structure including a cell substrate, a peripheral circuit structure overlapping the memory cell structure in a first direction perpendicular to an upper surface of the cell substrate, a plurality of semiconductor structures stacked in the first direction, and a plurality of through electrodes extending in the first direction in each of the plurality of semiconductor structures. The memory cell structure includes a semiconductor pattern including a channel region and a capacitor structure on one side of the semiconductor pattern, a plurality of memory cells stacked and spaced apart on the cell substrate in the first direction, a plurality of word lines extending in a second direction parallel to the upper surface of the cell substrate and surrounding the channel region, and a bit line on an opposite side of the semiconductor pattern.

What exactly they claim (claim 1)

1. A semiconductor memory device comprising: a plurality of semiconductor structures that are stacked in a first direction that is perpendicular to an upper surface of a cell substrate, each semiconductor structure of the plurality of semiconductor structures comprising (i) a memory cell structure including the cell substrate and (ii) a peripheral circuit structure that overlaps the memory cell structure in the first direction; and a plurality of through electrodes that extend in the first direction in each of the plurality of semiconductor structures, wherein the memory cell structure comprises: a plurality of memory cells that are stacked on the cell substrate and spaced apart in the first direction, each memory cell of the plurality of memory cells comprising a semiconductor pattern including a channel region and a capacitor structure on a first side of the semiconductor pattern, a plurality of word lines that extend in a second direction parallel to the upper surface of the cell substrate and that surround the channel region, and a bit line on a second side of the semiconductor pattern that is opposite to the first side of the semiconductor pattern.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
Publication number
US20260293161A1
Application number
19399357
Filed
Nov 24, 2025
Published
Sep 24, 2026
Inventors
2
Claims
20

Classified under

H10B 80/00 Electricity & electronicsH10B 12/30 Electricity & electronicsH10W 90/26 Electricity & electronicsH10W 90/291 Electricity & electronicsH10W 90/297 Electricity & electronicsH10W 90/724 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.