Samsung patents new method for building memory into 3D chip structures
Samsung describes a way to make 3D memory chips by etching holes in a stacked structure and filling them with different materials. This process creates data storage patterns and layers that sit between the chip's control gates and its central channel.
In the filing’s own words
The present disclosure provides methods, apparatuses, and systems for operating and manufacturing a semiconductor device. In some embodiments, a semiconductor device includes a stack structure including interlayer insulating layers and gate electrodes, a channel layer disposed inside a hole penetrating through the stack structure, a data storage layer disposed between the stack structure and the channel layer, data storage patterns disposed between the data storage layer and the gate electrodes, and dielectric layers disposed between the data storage patterns and the gate electrodes. The interlayer insulating layers and the gate electrodes are alternately and repeatedly stacked in a first direction. A first material of the data storage layer is different from a second material of the data storage patterns.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, the method comprising: forming a structure including interlayer insulating layers and sacrificial layers alternately and repeatedly stacked in a vertical direction; forming a hole penetrating the structure and exposing the interlayer insulating layers and the sacrificial layers; partially etching the sacrificial layers exposed by the hole to form expanded openings; forming data storage patterns in the expanded openings; forming a data storage layer in the hole, the data storage layer covering the data storage patterns and the interlayer insulating layers exposed by the hole; forming a channel layer in the hole, the channel layer covering the data storage layer; and forming an insulating core pattern in the hole, wherein the channel layer is between the data storage layer and the insulating core pattern.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE LAYER AND DATA STORAGE PATTERNS
- Publication number
- US20260293149A1
- Application number
- 19683128
- Filed
- May 20, 2026
- Published
- Sep 24, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10B 51/30 Electricity & electronicsH10B 41/10 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/35 Electricity & electronicsH10B 41/40 Electricity & electronicsH10B 43/10 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.