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Samsung patents memory chip design with stacked layers and new connection pads

Samsung describes a semiconductor memory device where the storage cells are stacked on top of a peripheral circuit layer. The design uses specific contact plugs and metal pads to connect the different layers, including a bypass via on the back of the chip.

Why it mattersThis filing focuses on the internal physical layout of memory chips, which is a routine improvement for engineers optimizing how data is stored and accessed in hardware.

In the filing’s own words

A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit and a first bonding pad, the first bonding pad connected to the peripheral circuit, a cell structure on the peripheral circuit structure, the cell structure including a second bonding pad bonded to the first bonding pad, and a pad structure on the cell structure. The cell structure includes a cell substrate having a first face, a second face opposite to the first face, a first contact plug extending through the cell substrate and connected to an electrode layer, and a second contact plug extending through the cell substrate and connected to the cell substrate. Each of the first contact plug and the second contact plug is connected to the pad structure, and a bypass via is in contact with the pad structure on the second face.

What exactly they claim (claim 1)

1. A semiconductor memory device comprising: a cell structure; and a pad structure on the cell structure, the cell structure including: a common source plate having a first face and a second face opposite to the first face, an electrode structure including a stack of a plurality of electrode layers on the first face of the common source plate, and a plurality of contact plugs between the first face and the second face of the common source plate, wherein the plurality of contact plugs includes a first contact plug connected to the common source plate, the pad structure includes a first metal pad and a second metal pad spaced apart from each other, and the first contact plug is connected to the first metal pad.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
Publication number
US20260293143A1
Application number
19686439
Filed
May 22, 2026
Published
Sep 24, 2026
Inventors
4
Claims
20

Classified under

H10B 43/40 Electricity & electronicsH10B 41/10 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/35 Electricity & electronicsH10B 41/40 Electricity & electronicsH10B 43/10 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.