Samsung patents memory chip design with varying gate widths
Samsung describes a method for making semiconductor devices where gate trenches have different widths. The wider trenches contain word lines with a lower impurity concentration than those in the narrower trenches.
In the filing’s own words
A method of manufacturing a semiconductor device may include forming a device isolation layer on a substrate and defining an active region of the substrate; forming gate trenches crossing the active region and the device isolation layer; and forming word line structures including word lines in the gate trenches. The gate trenches may include a first gate trench having a first width and a second gate trench having a second width greater than the first width. The word lines may include a first word line in the first gate trench and a second word line in the second gate trench. The first word line may include includes a first doped material having a first impurity concentration. The second word line may include a second doped material having a second impurity concentration. The second impurity concentration may be lower than the first impurity concentration.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, the method comprising: forming a substrate including an active region; forming a device isolation layer on the substrate and defining the active region; forming gate trenches crossing the active region and the device isolation layer, the gate trenches extending in a first horizontal direction; and forming word line structures including word lines in the gate trenches; wherein the gate trenches include a first gate trench having a first width and a second gate trench having a second width greater than the first width, the word lines include a first word line in the first gate trench and a second word line in the second gate trench, the first word line includes a first doped material having a first impurity concentration, the second word line includes a second doped material having a second impurity concentration, and the second impurity concentration is lower than the first impurity concentration.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE
- Publication number
- US20260293123A1
- Application number
- 19689182
- Filed
- May 27, 2026
- Published
- Sep 24, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10B 12/488 Electricity & electronicsH10B 12/34 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.