Samsung patents memory chip design with wider bit line ends
Samsung has filed a patent for a semiconductor device structure used in memory chips. The design features bit line structures that have a wider 'expansion part' at their ends, surrounded by specific spacer layers, to connect with active regions on the substrate.
In the filing’s own words
A semiconductor device, includes a substrate including a plurality of active regions, word lines, a buffer layer including first contact holes exposing active regions, first contacts in contact with the active regions through the first contact holes, bit line structures including first conductive layers in contact with the first contacts, bit line spacers that cover side surfaces of the bit line structures, and second contacts in contact with the plurality of active regions, the plurality of active regions including first parts and second parts on opposite sides of the word lines, in contact with the active regions,, each of the bit line structures including a main part and an expansion part, the bit line spacers including first, second and third spacers, and expansion spacers including fourth and fifth spacers.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate including a plurality of active regions; word lines in the substrate; a buffer layer on the substrate, the buffer layer including first contact holes therein exposing at least a subset of the plurality of active regions; first contacts that are in contact with the plurality of active regions through the first contact holes; bit line structures on the buffer layer, the bit line structures including first conductive layers which are in contact with the first contacts; bit line spacers that cover side surfaces of the bit line structures; and second contacts that are in contact with the plurality of active regions, wherein the plurality of active regions include first parts and second parts on opposite sides with respect to the word lines, the first contacts are in contact with the first parts of the plurality of active regions, the second contacts are in contact with the second parts of the plurality of active regions, each of the bit line structures includes a main part extending longitudinally, and an expansion part which is connected to an end of the main part, the expansion part configured to be wider than the main part as viewed in a plan view, the bit line spacers include main-part spacers including first spacers, second spacers, and third spacers arranged sequentially from side surfaces of the main parts of the bit line structures, and expansion spacers including fourth spacers and fifth spacers arranged sequentially from side surfaces of the expansion parts of the bit line structures.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- Publication number
- US20260293115A1
- Application number
- 19687507
- Filed
- May 26, 2026
- Published
- Sep 24, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 12/482 Electricity & electronicsH10B 12/03 Electricity & electronicsH10B 12/485 Electricity & electronicsH10W 20/056 Electricity & electronicsH10W 20/43 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.