Samsung patents memory chip design with stacked data storage layers
Samsung describes a structure for a semiconductor memory chip that uses a specific arrangement of electrodes and contact points to store data. The design places data storage patterns on landing pads above the main active areas, connected through a series of vertical and horizontal lines to manage data flow.
In the filing’s own words
A semiconductor memory device includes a substrate including a cell array region and a connection region, bit lines extended in a first direction, a first active pattern and a second active pattern disposed on each bit line, a back-gate electrode disposed between the first and second active patterns and extended in a second direction to cross the bit lines, a first word line disposed at a side of the first active pattern and extended in the second direction, a second word line disposed at an opposite side of the second active pattern and extended in the second direction, contact patterns coupled to the first and second active patterns, landing pads disposed on the contact patterns, data storage patterns disposed on the landing pads, bit line contact plugs on the connection region and coupled to the bit lines, and first peripheral interconnection lines connected to the bit line contact plugs.
What exactly they claim (claim 1)
1. A semiconductor memory device, comprising: a substrate including a cell array region and a connection region; bit lines provided on the substrate and extended in a first direction; a first active pattern and a second active pattern disposed on each of the bit lines; a back-gate electrode disposed between the first and second active patterns and extended in a second direction to cross the bit lines; a first word line disposed at a side of the first active pattern and extended in the second direction; a second word line disposed at an opposite side of the second active pattern and extended in the second direction; contact patterns coupled to the first and second active patterns, respectively; landing pads disposed on the contact patterns; data storage patterns disposed on the landing pads; bit line contact plugs on the connection region and coupled to the bit lines; and first peripheral interconnection lines connected to the bit line contact plugs.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR MEMORY DEVICE
- Publication number
- US20260293113A1
- Application number
- 19682840
- Filed
- May 20, 2026
- Published
- Sep 24, 2026
- Inventors
- 7
- Claims
- 20
Classified under
H10B 12/482 Electricity & electronicsH10B 12/315 Electricity & electronicsH10B 12/485 Electricity & electronicsH10B 12/488 Electricity & electronicsH10B 12/50 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.