Samsung patents chip design with flat, stacked contact points for memory
Samsung has filed a patent for an integrated circuit layout that arranges bit lines and electrical contacts in a specific, flat configuration. The design uses a two-part landing pad that sits flush with insulation layers and barrier materials to create a stable connection between different parts of the chip.
In the filing’s own words
An integrated circuit device includes a plurality of bit line structures on a substrate, each including an insulation capping pattern on a bit line; a buried contact between adjacent ones of the bit line structures; a barrier conductive layer along side surfaces of the insulation capping patterns and between the adjacent ones of the bit line structures; and a landing pad electrically connected to the buried contact and vertically overlapping a first one of the bit line structures, wherein the landing pad includes an upper landing pad portion on a lower landing pad portion, wherein uppermost surfaces of the insulation capping pattern of the first one of the bit line structures, the barrier conductive layer, and the lower landing pad portion are coplanar, and wherein the upper landing pad portion contacts the uppermost surfaces of the insulation capping pattern, the barrier conductive layer, and the lower landing pad portion.
What exactly they claim (claim 1)
1. An integrated circuit device, comprising: a substrate having an active area; a plurality of bit line structures on the substrate, each of the plurality of bit line structures including a bit line and an insulation capping pattern on the bit line; a buried contact between adjacent ones of the plurality of bit line structures, the buried contact being electrically connected to the active area; a barrier conductive layer disposed along side surfaces of the insulation capping patterns and extending into a space between the adjacent ones of the plurality of bit line structures; and a landing pad electrically connected to the buried contact and vertically overlapping a first one of the plurality of bit line structures, wherein the landing pad includes a lower landing pad portion and an upper landing pad portion on the lower landing pad portion, wherein an uppermost surface of the insulation capping pattern of the first one of the plurality of bit line structures, an uppermost surface of the barrier conductive layer, and an uppermost surface of the lower landing pad portion are coplanar with one another, and wherein the upper landing pad portion directly contacts the uppermost surface of the insulation capping pattern, the uppermost surface of the barrier conductive layer, and the uppermost surface of the lower landing pad portion.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- INTEGRATED CIRCUIT DEVICE
- Publication number
- US20260293112A1
- Application number
- 19681120
- Filed
- May 19, 2026
- Published
- Sep 24, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10B 12/482 Electricity & electronicsH10B 12/02 Electricity & electronicsH10B 12/315 Electricity & electronicsH10B 12/34 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.