Samsung patents 3D memory chip design with vertical seams
Samsung describes a method for building a memory chip where data storage units are stacked vertically to save space. The design uses a specific manufacturing step to create vertical gaps, or seams, in the insulating layers between the memory cells.
In the filing’s own words
A semiconductor device includes bit line structures on a substrate. Each bit line structure extends in a second direction, and the bit line structures are spaced apart from each other in a first direction. The semiconductor device further includes semiconductor patterns spaced apart from each other in the second direction on each of the bit line structures, insulating interlayer patterns between neighboring ones of the semiconductor patterns in the first direction, and word lines spaced apart from each other in the second direction on the bit line structures. Each word line extends in the first direction adjacent to the semiconductor patterns. The semiconductor device further includes capacitors disposed on and electrically connected to the semiconductor patterns, respectively. A seam extending in the second direction is formed in each of the insulating interlayer patterns.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, the method comprising: preparing a first substrate structure including a first substrate, a buried insulation structure and a semiconductor layer sequentially stacked; patterning the semiconductor layer to form preliminary semiconductor patterns, wherein each of the preliminary semiconductor patterns extends in a second direction parallel to an upper surface of the first substrate; forming a preliminary back gate electrode through the preliminary semiconductor patterns, wherein the preliminary back gate electrode extends in a first direction parallel to the upper surface of the first substrate and crossing the second direction; patterning the preliminary semiconductor patterns to form semiconductor patterns on opposite sides in the second direction of the preliminary back gate electrode; removing an upper portion of the preliminary back gate electrode to form a back gate electrode; forming a word line extending in the first direction adjacent to a sidewall of each of the semiconductor patterns; forming bit line structures on the semiconductor patterns, wherein each of the bit line structures extends in the second direction; removing the first substrate and the buried insulation structure to expose the semiconductor patterns; and forming capacitors on the semiconductor patterns, respectively.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
- Publication number
- US20260293098A1
- Application number
- 19692906
- Filed
- May 29, 2026
- Published
- Sep 24, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10B 12/315 Electricity & electronicsH10B 12/05 Electricity & electronicsH10B 12/482 Electricity & electronicsH10B 12/488 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.