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Samsung patents new wiring layout for memory chips

This filing describes a specific way to arrange metal wires and contact points on a semiconductor chip. It details how a third wire connects to the sides of vertical plugs that link to lower wires, creating a compact structure above the transistor area.

Why it mattersThis is a routine improvement in chip manufacturing that helps pack more components into a small space, which is standard practice for making faster and denser memory.

In the filing’s own words

A semiconductor device includes a peripheral circuit transistor disposed in a peripheral circuit region. First connection lines and second connection lines are disposed on a same plane above the peripheral circuit transistor. The second connection lines including a cutting portion. A cell capacitor is disposed on the substrate in a cell region. A first plate pattern is on the cell capacitor. A second plate pattern is on a portion of a surface of the first plate pattern. A first contact plug directly contacts an upper surface of the second plate pattern. A third connection line is disposed above the second connection line. The third connection line faces the cutting portion. Second contact plugs extend vertically to directly contact both sidewalls of the third connection line and upper surfaces of the second connection lines. The third connection line is disposed on a same plane as the second plate pattern.

What exactly they claim (claim 1)

1. A semiconductor device, comprising: a first connection line on a substrate; a second connection line on the substrate; a first contact plug contacting an upper surface of the first connection line; a second contact plug contacting an upper surface of the second connection line; and a third connection line contacting a sidewall of the first contact plug and a sidewall of the second contact plug together to connect to the first contact plug and the second contact plug, wherein the third connection line disposed above upper surfaces of the first connection line and the second connection line.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
SEMICONDUCTOR DEVICE
Publication number
US20260293096A1
Application number
19677762
Filed
May 14, 2026
Published
Sep 24, 2026
Inventors
4
Claims
20

Classified under

H10B 12/315 Electricity & electronicsH10B 12/482 Electricity & electronicsH10B 12/50 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.