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Samsung patents 3D memory stack with uneven layer spacing

Samsung describes a design for 3D memory chips where layers of storage cells are stacked vertically. The filing specifies that the vertical gap between the main data channels is larger than the gap between the control lines, a specific arrangement within the chip's internal structure.

Why it mattersThis is a routine engineering adjustment to memory chip architecture that may help improve manufacturing yield or performance, but it is too technical for most consumers to notice directly.

In the filing’s own words

A semiconductor memory device, comprising a stack structure including layer groups stacked on a substrate, each including a word line, a channel layer, and a data storage element; and a bit line extending in the vertical direction on one side of the stack structure, wherein the word line of each layer group extends in a first direction parallel to the top surface of the substrate, the channel layer of each layer group extends in a second direction, and the channel layers of first and second layer groups vertically overlap the word lines of the first and second layer groups, respectively. A first vertical interval between the channel layers of the first and second layer groups is greater than a second vertical interval between a bottom surface of the word line of the first layer group and a top surface of the word line of the second layer group.

What exactly they claim (claim 1)

1. A semiconductor memory device, comprising: a stack structure including layer groups that are stacked on a substrate in a vertical direction perpendicular to a top surface of the substrate, the layer groups each including a word line, a channel layer, and a data storage element that is electrically connected to the channel layer; and a bit line on one side of the stack structure, the bit line extending lengthwise in the vertical direction, wherein the word line of each of the layer groups extends in a first direction parallel to the top surface of the substrate, wherein the channel layer of each of the layer groups extends in a second direction crossing the first direction, wherein the layer groups include a first layer group and a second layer group stacked on the first layer group in the vertical direction, wherein the channel layer of the first layer group vertically overlaps the word line of the first layer group, wherein the channel layer of the second layer group vertically overlaps the word line of the second layer group, and wherein a first vertical interval between the channel layer of the first layer group and the channel layer of the second layer group is greater than a second vertical interval between a bottom surface of the word line of the first layer group and a top surface of the word line of the second layer group.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
Publication number
US20260293090A1
Application number
19686764
Filed
May 24, 2026
Published
Sep 24, 2026
Inventors
6
Claims
20

Classified under

H10B 12/30 Electricity & electronicsH10B 12/05 Electricity & electronicsH10B 12/50 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.