Samsung patents 3D memory layout with local and global data paths
Samsung describes a method for organizing 3D memory into sections, each with specific row and column dimensions. The design uses local and global input/output lines connected by switches to route data between memory cells and the rest of the circuit.
In the filing’s own words
A system and a method for organizing a 3D memory circuit are disclosed. The 3D memory circuit includes a memory array and an activation circuit. The memory array is configured to be organized into N sections. Each section has a row dimension K, a column dimension L, and a word line (WL) connected to L memory cells. The activation circuit is configured to activate, in response to an activation, the WL to generate an activated WL. Each section includes a transfer circuit including a data switch and a select switch. The data switch is configured to route data between a local input/output (LIO) line and a global input/output (GIO) line. The select switch is configured to connect the LIO line to a bit line (BL) by a column select (CS) signal. The BL is connected to one of the L memory cells which is connected to the activated WL.
What exactly they claim (claim 1)
1. A device comprising: a memory array configured to be organized into N sections, each section having a row dimension K, a column dimension L, and a word line (WL) connected to L memory cells, wherein K, L, and N are positive integers; an activation circuit configured to activate, in response to an activation, the WL to generate an activated WL; and each section including a transfer circuit comprising: a data switch configured to route data between a local input/output (LIO) line and a global input/output (GIO) line, and a select switch configured to connect the LIO line to a bit line (BL) by a column select (CS) signal, the BL being connected to one of the L memory cells, the one of the L memory cells being connected to the activated WL.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- ARRAY ORGANIZATION IN THREE-DIMENSIONAL MEMORY CIRCUITS
- Publication number
- US20260290437A1
- Application number
- 19449400
- Filed
- Jan 14, 2026
- Published
- Sep 24, 2026
- Inventors
- 3
- Claims
- 20
Classified under
G11C 11/4096 Physics & computingG11C 11/4085 Physics & computingG11C 11/4091 Physics & computingG11C 11/4094 Physics & computingMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.