Samsung patents chip layout with extra wall around memory cells
Samsung describes a method for building integrated circuits by digging trenches in a silicon base to create a physical barrier called an active dam. This dam surrounds the memory cell area, separating it from the rest of the chip using different types of insulating films.
In the filing’s own words
A method of manufacturing an integrated circuit device includes forming a preliminary trench in a core area of a substrate; forming a first trench, a second trench, and a third trench in the substrate to form an active dam between the second trench and the third trench, wherein the first trench is formed in a cell array area of the substrate, the cell array area being spaced apart from the core area, the second trench is formed from the preliminary trench in the core area, the third trench is formed in an interface area of the substrate, the interface area being between the cell array area and the core area, and the active dam surrounds the cell array area in a plan view; and forming a cell device isolation film filling the first trench, a peripheral device isolation film filling the second trench, and an interface device isolation film filling the third trench. At least a portion of the active dam is in the core area, and the active dam is spaced apart from the cell array area with the interface device isolation film therebetween.
What exactly they claim (claim 1)
1. A method of manufacturing an integrated circuit device, the method comprising: forming a preliminary trench in a core area of a substrate; forming a first trench, a second trench, and a third trench in the substrate to form an active dam between the second trench and the third trench, wherein the first trench is formed in a cell array area of the substrate, the cell array area being spaced apart from the core area, the second trench is formed from the preliminary trench in the core area, the third trench is formed in an interface area of the substrate, the interface area being between the cell array area and the core area, and the active dam surrounds the cell array area in a plan view; and forming a cell device isolation film filling the first trench, a peripheral device isolation film filling the second trench, and an interface device isolation film filling the third trench, wherein at least a portion of the active dam is in the core area, and the active dam is spaced apart from the cell array area with the interface device isolation film therebetween.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- INTEGRATED CIRCUIT DEVICE
- Publication number
- US20260290427A1
- Application number
- 19687770
- Filed
- May 26, 2026
- Published
- Sep 24, 2026
- Inventors
- 9
- Claims
- 20
Classified under
G11C 11/4085 Physics & computingG11C 5/063 Physics & computingG11C 11/4091 Physics & computingH10B 12/482 Electricity & electronicsH10B 12/485 Electricity & electronicsH10B 12/488 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.