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Microsoft patents faster hardware method for reading text

Microsoft describes a hardware design that speeds up how computers read and understand text by processing multiple characters at once. The system uses a specific circuit layout to guess the next step in reading without waiting for previous calculations to finish, which helps the processor keep up with fast data streams.

Why it mattersThis improves the raw speed of basic text processing in computer chips, which is a routine but necessary upgrade for handling large amounts of data efficiently.

In the filing’s own words

The performance of a text parser implemented with a state machine is improved by reducing a critical dependence path. In one aspect, all possible current states for a given text input are read from a state table circuit, and the correct next state and output are then selected therefrom by an output multiplexer based on the current state, removing dependence on the current state from the table read, and allowing the read(s) to be pipelined. Further, multiple input units are configured to operate on multiple text characters in parallel, with each input unit propagating outputs for its state table circuit to the next downstream input unit. Each downstream input unit is configured to use the propagated states to provide the proper outputs to appropriates multiplexer inputs. The number of possible output states may be dynamically reduced, thereby reducing the size of the output multiplexer needed to select the next state.

What exactly they claim (claim 1)

1. A circuit-implemented method for processing input characters in parallel by a text parser, comprising: receiving a stream of text characters in sequence comprising a first character and a second character; generating, without a value of a current state of the text parser as input and by a first set of state table circuits that each correspond to a predetermined state of a set of predetermined states, first state table circuit outputs based on the first character and the corresponding predetermined state of the set of predetermined states, wherein the first state table circuit outputs corresponding to each state table circuit of the first set of state table circuits comprise a first set of state table circuit outputs; identifying, within a second set of state table circuits that each correspond to a predetermined state of the set of predetermined states, an invalid input to the second set of state table circuits; generating, without the value of the current state as input and by the second set of state table circuits, second state table circuit outputs based on the second character, at least one of the corresponding predetermined state of the set of predetermined states, and said identifying the invalid input; selecting a first text parser output from among the first set of state table circuit outputs based on the current state; selecting which of respective outputs of the second set of state table circuit outputs to route as a set of state propagator outputs based on the first set of state table circuit outputs; and selecting a second text parser output from among the set of state propagator outputs based on the current state.

Facts

Company
Microsoft (Microsoft Technology Licensing, LLC)
Official title
HIGH-PERFORMANCE MICROCODED TEXT PARSER
Publication number
US20260289110A1
Application number
19692704
Filed
May 29, 2026
Published
Sep 24, 2026
Inventors
2
Claims
20

Classified under

G06F 40/205 Physics & computingG06F 16/83 Physics & computingH03K 19/1737 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.