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GooglePatent applicationChips & hardwareInterest 4/10

Google patents memory layout that stacks chips to save space

Google describes a way to fit more memory into a computer by stacking multiple memory connection layers on top of each other. Instead of spreading these connections out along the processor's edge, they are layered to occupy the same physical space as a single connection. This allows the device to support larger amounts of memory without needing a wider processor.

Why it mattersIt is an engineering improvement that helps computer makers pack more memory into tight spaces, which is useful for devices like servers or compact laptops.

In the filing’s own words

A memory subsystem in a compute device includes a number of memory controllers in combination with one or more physical layers (PHY). A processor of the device adjacent to the memory controllers communicates processing commands for memory requests with the MCs that manages the reading and writing of data from memory via the PHY. The width of the PHY defines the amount of space required by the memory subsystem along an edge of the processor. A number PHY are accommodated within the space of one PHY beachfront through stacking PHY with respect to the memory controllers. Tunnels are provided across the PHY passing between I/O pads of the PHY that connect distant PHY to the memory controllers. The compute device can utilize larger amounts of memory supporting multiple PHY in the space of one memory subsystem.

What exactly they claim (claim 1)

1. A compute device comprising: a processor; a plurality of memory channels in communication with the processor, each memory channel comprising: a memory controller (MC) in communication with the processor; and a physical layer (PHY) associated with the MC of the memory channel; wherein a plurality of PHY layers for a plurality of the memory channels are stacked widthwise to produce a beachfront for the plurality of PHY layers that takes up a space of a single PHY at an edge of the processor.

Facts

Company
Google (Google LLC)
Official title
Multiple DDR Subsystems With Single Beachfront Using Chained PHYs
Publication number
US20260288333A1
Application number
19088138
Filed
Mar 24, 2025
Published
Sep 24, 2026
Inventors
2
Claims
20

Classified under

G06F 3/061 Physics & computingG06F 3/0631 Physics & computingG06F 3/0683 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.