Samsung patents stacked chip design with uneven top surfaces
Samsung describes a method for building a semiconductor package by stacking two chips vertically. The process involves embedding the bottom chip in a protective layer, thinning that layer so the chip sits slightly lower than the surrounding material, and then placing the top chip on a protective coating above it.
In the filing’s own words
A method of fabricating a semiconductor package comprises: mounting a lower semiconductor chip on a first redistribution substrate; placing a lower post on the first redistribution substrate; forming on the first redistribution substrate a lower molding layer that covers the lower semiconductor chip and the lower post; performing a thinning process on the lower molding layer to expose top surfaces of the lower semiconductor chip and the lower post, wherein the thinning process causes the top surface of the lower semiconductor chip to be lower than a top surface of the lower molding layer; forming a passivation layer on the top surface of the lower molding layer and the top surface of the lower semiconductor chip; placing an upper semiconductor chip on the passivation layer over the lower semiconductor chip; and forming on the passivation layer an upper molding layer that covers the upper semiconductor chip.
What exactly they claim (claim 1)
1. A method of fabricating a semiconductor package, the method comprising: mounting a lower semiconductor chip on a first redistribution substrate; placing a lower post on the first redistribution substrate; forming on the first redistribution substrate a lower molding layer that covers the lower semiconductor chip and the lower post; performing a thinning process on the lower molding layer to expose a top surface of the lower semiconductor chip and a top surface of the lower post, wherein the thinning process causes the top surface of the lower semiconductor chip to be lower than a top surface of the lower molding layer; forming a passivation layer on the top surface of the lower molding layer and the top surface of the lower semiconductor chip; placing an upper semiconductor chip on the passivation layer over the lower semiconductor chip; and forming on the passivation layer an upper molding layer that covers the upper semiconductor chip.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
- Publication number
- US20260283050A1
- Application number
- 19675355
- Filed
- May 12, 2026
- Published
- Sep 17, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10W 90/701 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 74/016 Electricity & electronicsH10W 74/019 Electricity & electronicsH10W 72/07253 Electricity & electronicsH10W 72/232 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.