Samsung patents stacked chip design with aligned edges
Samsung describes a method for building semiconductor packages by stacking chips on top of one another. The process involves cutting a wafer to create a base chip with specific internal connections, then placing additional chips and protective layers on top to form a compact unit.
In the filing’s own words
A method of fabricating semiconductor package, includes mounting a second semiconductor chip on a wafer, forming a second molding layer surrounding the second semiconductor chip on the wafer, forming a preliminary package by performing a cutting process of cutting the wafer and the second molding layer, the cut wafer constitutes a first semiconductor chip, mounting the preliminary package on a first redistribution substrate, mounting a third semiconductor chip on the second semiconductor chip, and forming a second redistribution substrate on the third semiconductor chip, the first semiconductor chip including a through via that extends into the first semiconductor chip, and a side surface of the first semiconductor chip being vertically aligned with a side surface of the second molding layer by the cutting process.
What exactly they claim (claim 1)
1 - 20. (canceled)
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGES
- Publication number
- US20260283034A1
- Application number
- 19673135
- Filed
- May 11, 2026
- Published
- Sep 17, 2026
- Inventors
- 3
- Claims
- 21
Classified under
H10W 90/00 Electricity & electronicsH10W 20/20 Electricity & electronicsH10W 70/611 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 72/20 Electricity & electronicsH10W 72/30 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.