Samsung patents stacked chip design with vertical wiring layers
Samsung describes a semiconductor package that stacks multiple chips in two separate groups, or sub-stacks, between two flat connection boards called redistribution substrates. Vertical wires connect the chips in each group to their respective boards, allowing signals to travel up and down through the structure.
In the filing’s own words
Provided is a semiconductor package including a first redistribution substrate, a chip stacked structure including a first sub-stack and a second sub-stack arranged on the first sub-stack, wherein the first sub-stack and the second sub-stack includes a plurality of semiconductor chips respectively, a second redistribution substrate arranged on the chip stacked structure, a first sub-stack vertical wiring unit including vertical wires configured to connect each of the semiconductor chips constituting the first sub-stack to the first redistribution substrate and extend to an upper surface of the first redistribution substrate in a vertical direction, and a second sub-stack vertical wiring unit including vertical wires configured to connect each of the semiconductor chips constituting the second sub-stack to the second redistribution substrate and extend to a lower surface of the second redistribution substrate in the vertical direction.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a first redistribution substrate; a chip stacked structure including a first sub-stack and a second sub-stack arranged on the first sub-stack, wherein the first sub-stack is arranged apart from the first redistribution substrate above the first redistribution substrate and includes a plurality of semiconductor chips that are stacked, and the second sub-stack includes a plurality of semiconductor chips that are stacked; a second redistribution substrate arranged on the chip stacked structure; a first sub-stack vertical wiring unit including vertical wires configured to connect each of the semiconductor chips constituting the first sub-stack to the first redistribution substrate and extend to an upper surface of the first redistribution substrate in a vertical direction; and a second sub-stack vertical wiring unit including vertical wires configured to connect each of the semiconductor chips constituting the second sub-stack to the second redistribution substrate and extend to a lower surface of the second redistribution substrate in the vertical direction.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKGE
- Publication number
- US20260283018A1
- Application number
- 19313286
- Filed
- Aug 28, 2025
- Published
- Sep 17, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10W 90/00 Electricity & electronicsH10B 80/00 Electricity & electronicsH10D 80/30 Electricity & electronicsH10W 40/258 Electricity & electronicsH10W 42/60 Electricity & electronicsH10W 70/611 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.