Samsung patents chip package with textured base for better shielding
This filing describes a semiconductor package design that includes an electromagnetic wave shielding layer to protect the chip. The base of the package features a lower surface with two different levels of roughness, where the smoother area is positioned away from the connection points.
In the filing’s own words
A semiconductor package includes a package substrate including a substrate base, an upper solder resist layer covering the upper surface of the substrate base, and a lower solder resist layer covering the lower surface of the substrate base, at least one semiconductor chip attached onto the package substrate, a molding layer covering the upper surface of the package substrate and surrounding the at least one semiconductor chip, and an electromagnetic wave shielding layer covering the package substrate and the molding layer, in which a lower surface of the lower solder resist layer has a first lower surface region having a first arithmetic average roughness and a second lower surface region having a second arithmetic average roughness that is less than the first arithmetic average roughness.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a package substrate including a substrate base, a plurality of upper surface connection pads disposed on an upper surface of the substrate base, a plurality of lower surface connection pads disposed on a lower surface of the substrate base and electrically connected to the plurality of corresponding upper surface connection pads, an upper solder resist layer covering the upper surface of the substrate base, and a lower solder resist layer covering the lower surface of the substrate base; at least one semiconductor chip attached onto the package substrate and electrically connected to the plurality of upper surface connection pads; a plurality of package connection terminals respectively attached onto the plurality of lower surface connection pads; a molding layer covering the upper surface of the package substrate and surrounding the at least one semiconductor chip; and an electromagnetic wave shielding layer covering the package substrate and the molding layer, wherein a lower surface of the lower solder resist layer has a first lower surface region having a first arithmetic average roughness and a second lower surface region having a second arithmetic average roughness that is less than the first arithmetic average roughness, and the first lower surface region is spaced apart from the plurality of package connection terminals and disposed along an edge of the package substrate.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME
- Publication number
- US20260282984A1
- Application number
- 19564638
- Filed
- Mar 12, 2026
- Published
- Sep 17, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 70/687 Electricity & electronicsH10W 42/276 Electricity & electronicsH10W 70/654 Electricity & electronicsH10W 90/7295 Electricity & electronicsH10W 72/884 Electricity & electronicsH10W 74/15 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.