Samsung patents chip package design with stacked layers and side wiring
Samsung describes a semiconductor package that stacks chips on a base board with wiring on both the top and bottom surfaces. The design uses vertical connections to link the layers while keeping the main chips separated from the central wiring paths.
In the filing’s own words
A fan-out semiconductor package includes a wiring substrate including a first fan-in region, a fan-out region surrounding the first fan-in region, and a second fan-in region, a first fan-in chip structure, a second fan-in chip structure, a first redistribution structure including first redistribution elements disposed on a bottom surface of the wiring substrate, and a second redistribution structure disposed on a top surface of the wiring substrate, and a chip wiring structure formed on a top surface of the second chip, and the second redistribution structure includes a second redistribution layer extending to the first fan-in region and the fan-out region, a plurality of second redistribution vias integrally formed with the second redistribution layer and extending downward, and a seed layer surrounding the second redistribution layer and bottom surfaces of the plurality of second redistribution vias.
What exactly they claim (claim 1)
1. A fan-out semiconductor package comprising: a first redistribution structure; a second redistribution structure on the first redistribution structure; a plurality of conductive vias between the first redistribution structure and the second redistribution structure, the plurality of conductive vias electrically connecting the first redistribution structure and the second redistribution structure; a first chip structure on the first redistribution structure in a first fan-in region in a plan view; a second chip structure on the first redistribution structure in a second fan-in region spaced apart from the first fan-in region in the plan view; and an encapsulation layer on the first chip structure and the second chip structure, wherein the first fan-in region and the second fan-in region are each spaced apart from the plurality of conductive vias, wherein the first chip structure comprises a first chip on the first redistribution structure, a second chip on the first chip, and a chip wiring structure on the second chip, and wherein the second redistribution structure comprises a plurality of second redistribution vias, a second redistribution layer, and a redistribution insulating layer.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- SEMICONDUCTOR PACKAGE
- Publication number
- US20260282983A1
- Application number
- 19673390
- Filed
- May 11, 2026
- Published
- Sep 17, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10W 70/685 Electricity & electronicsH10W 70/635 Electricity & electronicsH10W 74/117 Electricity & electronicsH10W 70/655 Electricity & electronicsH10W 72/07253 Electricity & electronicsH10W 72/07353 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.