Samsung patents chip package design with specific edge spacing
Samsung has filed a patent for a semiconductor package that arranges passive components on a substrate using specific solder connections. The design features lands with one edge touching a protective layer and the opposite edge spaced away from it to secure the components.
In the filing’s own words
Example embodiments of the present disclosure provides a semiconductor package including: a substrate including a plurality of lands, and conductive traces connected to at least one side of each of the plurality of lands; a solder resist layer covering the plurality of lands and at least a portion of the conductive traces; a passive component including a plurality of electrodes disposed on the solder resist layer and electrically connected to the plurality of lands; and solder members connecting the plurality of electrodes and the plurality of lands, respectively, and each of the plurality of lands includes a connection edge to which the conductive traces are connected, and a non-connection edge, other than the connection edge, the connection edge is in contact with the solder resist layer, and the non-connection edge is spaced apart from the solder resist layer.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a substrate including a plurality of lands, and conductive traces connected to at least one side of each of the plurality of lands; a solder resist layer covering at least a portion of each of the plurality of lands and the conductive traces; a passive component disposed on the solder resist layer and including a plurality of electrodes connected to the plurality of lands; and solder members connecting the plurality of electrodes and the plurality of lands, respectively, wherein: each of the plurality of lands includes a connection edge to which one of the conductive traces is connected, and a non-connection edge, other than the connection edge, the connection edge is in contact with the solder resist layer, and the non-connection edge is spaced apart from the solder resist layer.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE
- Publication number
- US20260282970A1
- Application number
- 19327976
- Filed
- Sep 12, 2025
- Published
- Sep 17, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10W 70/65 Electricity & electronicsH10W 70/635 Electricity & electronicsH10W 74/117 Electricity & electronicsH10W 90/701 Electricity & electronicsH10W 90/724 Electricity & electronicsH10W 90/754 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.