Samsung patents chip package design using bridge die and vertical posts
Samsung describes a semiconductor package that uses a 'bridge die' and vertical connection posts to link chips to the base. The design includes specific solder connections and insulating layers to manage electrical paths within the package.
In the filing’s own words
A semiconductor package includes a bridge die; an encapsulant; a redistribution structure including redistribution patterns and an upper insulating layer; semiconductor chips disposed on the redistribution structure and electrically connected to the redistribution patterns; connection posts extending in a vertical direction in the encapsulant and electrically connected to the redistribution patterns; and a plurality of connection conductor structures below the bridge die and the connection posts, wherein the plurality of connection conductor structures include a first group of the plurality of connection conductor structures overlapping the bridge die, and a second group of the plurality of connection conductor structures overlapping the connection posts, wherein each of the first group of the plurality of connection conductor structures includes a connection pad; an upper connection solder in contact with and electrically connected to the bridge die on the connection pad; and a lower connection solder below the connection pad.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a bridge die; an encapsulant that surrounds the bridge die; a redistribution structure on the encapsulant and comprising redistribution patterns electrically connected to the bridge die and an upper insulating layer surrounding the redistribution patterns; semiconductor chips on the redistribution structure and electrically connected to the redistribution patterns; connection posts that extend in a vertical direction in the encapsulant and electrically connected to the redistribution patterns; and a plurality of connection conductor structures below the bridge die and the connection posts, wherein the plurality of connection conductor structures comprise a first group of the plurality of connection conductor structures that overlap the bridge die, and a second group of the plurality of connection conductor structures that overlap the connection posts, and wherein each connection conductor structure of the first group of the plurality of connection conductor structures comprises: a connection pad; an upper connection solder in contact with and electrically connected to the bridge die on the connection pad; and a lower connection solder below the connection pad.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
- Publication number
- US20260282955A1
- Application number
- 19398775
- Filed
- Nov 24, 2025
- Published
- Sep 17, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10W 70/618 Electricity & electronicsH10W 70/635 Electricity & electronicsH10W 70/65 Electricity & electronicsH10W 72/823 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.