Samsung patents chip stacking method using interlocking key patterns
Samsung describes a way to stack two semiconductor chips vertically by using a specific pattern of metal connections. The design uses inner and outer 'key' shapes that fit together like puzzle pieces to hold the chips in place during manufacturing.
In the filing’s own words
A semiconductor package according to embodiments includes a first semiconductor die and a second semiconductor die on the first semiconductor die, the first semiconductor die comprising: a first die base; a first bonding dielectric layer on a back side of the first die base; a plurality of first key patterns penetrating the first bonding dielectric layer; and a plurality of second key patterns penetrating the first bonding dielectric layer, each second key pattern surrounding a corresponding first key pattern of the plurality of first key patterns, the second semiconductor die comprising: a second die base; a second bonding dielectric layer disposed on a front side of the second die base and bonded to the first bonding dielectric layer; a plurality of third key patterns penetrating the second bonding dielectric layer, each third key pattern bonding to a corresponding first key pattern of the plurality of first key patterns; and a plurality of fourth key patterns penetrating the second bonding dielectric layer, each fourth key pattern surrounding a corresponding third key pattern of the plurality of third key patterns and bonding to a corresponding second key pattern of the plurality of second key patterns, wherein: each of the plurality of first key patterns has a first width in a horizontal direction, each of the plurality of second key patterns has a second width in the horizontal direction, each of the plurality of third key patterns has a third width in the horizontal direction, each of the plurality of fourth key patterns has a fourth width in the horizontal direction, the first width is smaller than the third width, and the second width is larger than the fourth width.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a first semiconductor die and a second semiconductor die on the first semiconductor die, the first semiconductor die comprising: a first die base; a first bonding dielectric layer on a back side of the first die base; a plurality of first key patterns penetrating the first bonding dielectric layer; and a plurality of second key patterns penetrating the first bonding dielectric layer, each second key pattern surrounding a corresponding first key pattern of the plurality of first key patterns, the second semiconductor die comprising: a second die base; a second bonding dielectric layer disposed on a front side of the second die base and bonded to the first bonding dielectric layer; a plurality of third key patterns penetrating the second bonding dielectric layer, each third key pattern bonding to a corresponding first key pattern of the plurality of first key patterns; and a plurality of fourth key patterns penetrating the second bonding dielectric layer, each fourth key pattern surrounding a corresponding third key pattern of the plurality of third key patterns and bonding to a corresponding second key pattern of the plurality of second key patterns, wherein: each of the plurality of first key patterns has a first width in a horizontal direction, each of the plurality of second key patterns has a second width in the horizontal direction, each of the plurality of third key patterns has a third width in the horizontal direction, each of the plurality of fourth key patterns has a fourth width in the horizontal direction, the first width is smaller than the third width, and the second width is larger than the fourth width.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
- Publication number
- US20260282937A1
- Application number
- 19378498
- Filed
- Nov 4, 2025
- Published
- Sep 17, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10W 46/00 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 46/301 Electricity & electronicsH10W 72/923 Electricity & electronicsH10W 72/926 Electricity & electronicsH10W 72/932 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.