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Samsung patents stacking chips with heat-fused metal pads

Samsung describes a method for building semiconductor packages by stacking chips vertically. The process uses heat to fuse metal pads on the chips together into single layers, creating a compact structure without traditional solder joints.

Why it mattersThis technique could help manufacturers create smaller, more efficient processors by stacking components tightly.

In the filing’s own words

A method of fabricating a semiconductor package may include: bringing a first semiconductor chip in to contact with a semiconductor substrate such that a first chip pad is vertically aligned to a substrate pad; performing a first thermal treatment process on the semiconductor substrate and the first semiconductor chip; providing a second semiconductor chip including a second chip pad; bringing a third semiconductor chip into contact with the second semiconductor chip such that the second chip pad is vertically aligned to the third chip pad; bonding the third semiconductor chip to the second semiconductor chip by performing a second thermal treatment process on the second semiconductor chip and the third semiconductor chip to form a first chip structure; and mounting the first chip structure on the first semiconductor chip using first connection terminals, the first connection terminals connect the second semiconductor chip and the first semiconductor chip.

What exactly they claim (claim 1)

1. A method of fabricating a semiconductor package, comprising: providing a semiconductor substrate comprising a substrate pad; providing a first semiconductor chip comprising a first chip pad; bringing the first semiconductor chip in to contact with the semiconductor substrate such that the first chip pad is vertically aligned to the substrate pad; performing a first thermal treatment process on the semiconductor substrate and the first semiconductor chip to bond the first semiconductor chip to the semiconductor substrate; providing a second semiconductor chip comprising a second chip pad; providing a third semiconductor chip comprising a third chip pad; bringing the third semiconductor chip into contact with the second semiconductor chip such that the second chip pad is vertically aligned to the third chip pad; bonding the third semiconductor chip to the second semiconductor chip by performing a second thermal treatment process on the second semiconductor chip and the third semiconductor chip to form a first chip structure; and mounting the first chip structure on the first semiconductor chip using first connection terminals, the first connection terminals connect the second semiconductor chip of the first chip structure and the first semiconductor chip, wherein the substrate pad and the first chip pad each comprise a same metallic material and form a first single structure or layer by the first thermal treatment process, and wherein the second chip pad and the third chip pad form a second single structure or layer, which is formed of the same metallic material as the substrate pad, by the second thermal treatment process.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
Publication number
US20260282924A1
Application number
19667049
Filed
May 4, 2026
Published
Sep 17, 2026
Inventors
1
Claims
20

Classified under

H10W 42/121 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 20/20 Electricity & electronicsH10W 70/635 Electricity & electronicsH10W 74/117 Electricity & electronicsH10W 72/07353 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.