Samsung patents stacked memory design with protective fill
Samsung describes a method for building memory chips by stacking two semiconductor layers on top of each other. The design uses a protective coating that fills in small gaps around vertical connections to secure the stacked components.
In the filing’s own words
A semiconductor memory device includes a first semiconductor structure including a first semiconductor substrate and a first semiconductor element layer on a first surface of the first semiconductor substrate, and a second semiconductor structure on the first semiconductor structure, the second semiconductor structure including a second semiconductor substrate and a second semiconductor element layer on a second surface of the second semiconductor substrate. The second semiconductor structure includes a first via structure vertically penetrating the second semiconductor substrate and connected to the second semiconductor element layer, the first via structure is exposed on a third surface of the second semiconductor substrate, and a passivation layer covering the third surface. The second semiconductor substrate includes a recess region provided on the third surface and surrounding the first via structure. The passivation layer includes a protrusion fills the recess region. The passivation layer is in contact with the first via structure.
What exactly they claim (claim 1)
1. A semiconductor memory device comprising: a first semiconductor structure including a first semiconductor substrate and a first semiconductor element layer on a first surface of the first semiconductor substrate; and a second semiconductor structure on the first semiconductor structure, the second semiconductor structure including a second semiconductor substrate and a second semiconductor element layer on a second surface of the second semiconductor substrate, wherein the second semiconductor structure comprises: a first via structure extending vertically in the second semiconductor substrate and connected to the second semiconductor element layer; and a passivation layer covering a third surface of the second semiconductor substrate, wherein the third surface is opposite the second surface, wherein the second semiconductor substrate defines a recess region on the third surface, wherein the recess region surrounds the first via structure, and wherein the passivation layer includes a protrusion that fills the recess region, the passivation layer being in contact with the first via structure.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR MEMORY DEVICE
- Publication number
- US20260282870A1
- Application number
- 19419372
- Filed
- Dec 15, 2025
- Published
- Sep 17, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 20/213 Electricity & electronicsH10B 12/315 Electricity & electronicsH10B 12/482 Electricity & electronicsH10B 12/488 Electricity & electronicsH10D 80/30 Electricity & electronicsH10W 72/9226 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.