Samsung patents chip design with uneven gate shapes for better performance
This filing describes a method for building a semiconductor device where the internal gate structures have different shapes. The process uses specific etching steps to create a convex shape on one part of the gate, which helps control how electricity flows through the tiny transistors.
In the filing’s own words
A semiconductor device comprises a substrate including NMOSFET and PMOSFET regions, first and second channel patterns on the NMOSFET and PMOSFET regions, respectively, and each including respective semiconductor patterns spaced apart from and vertically stacked on each other, first and second source/drain patterns on the NMOSFET and NMOSFET regions and connected to the first and second channel patterns, respectively, and a gate electrode on the first and second channel patterns. The gate electrode includes a first inner electrode between neighboring semiconductor patterns of the first channel pattern, and a second inner electrode between neighboring semiconductor patterns of the second channel pattern. A top surface of the first inner electrode is more convex than a top surface of the second inner electrode.
What exactly they claim (claim 1)
1. A method of fabricating a semiconductor device, the method comprising: forming a stack pattern on a substrate, the stack pattern including active layers and sacrificial layers that are alternately stacked on the substrate; forming a sacrificial pattern on the stack pattern, the sacrificial pattern extending in a first direction; using the sacrificial pattern as a mask to etch the stack pattern to form a recess in the stack pattern, such that the active layers of the stack pattern each include neighboring semiconductor patterns that are exposed by the recess; performing a selective epitaxial growth process in which the neighboring semiconductor patterns exposed by the recess are used as a seed to form a source/drain pattern that fills the recess; removing the sacrificial pattern and the sacrificial layers to form an inner region between the neighboring semiconductor patterns; forming a spacer layer to partially fill the inner region; performing a dry etching process on the spacer layer to reduce a thickness in a vertical direction of the spacer layer; performing a wet etching process on the spacer layer to expose the neighboring semiconductor patterns; and forming an inner electrode in the inner region, wherein the wet etching process over-etches the neighboring semiconductor patterns to cause the inner region to have a convex floor and a convex ceiling.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
- Publication number
- US20260282533A1
- Application number
- 19669564
- Filed
- May 6, 2026
- Published
- Sep 17, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10D 84/85 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 62/151 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.