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Samsung patents stacked chips with layered transistors

Samsung describes a semiconductor package where two logic chips are stacked vertically on top of each other. Each chip contains transistors built in two layers, with upper and lower channel structures overlapping to save space.

Why it mattersThis design helps pack more computing power into a smaller area, which is important for making phones and computers more efficient.

In the filing’s own words

A semiconductor package may include a first logic chip, and a second logic chip overlapping with the first logic chip. The first logic chip may include a first lower channel structure, a first lower source/drain pattern connected to the first lower channel structure, a first upper channel structure overlapping with the first lower channel structure, and a first upper source/drain pattern connected to the first upper channel structure. The second logic chip may include a second lower channel structure, a second lower source/drain pattern connected to the second lower channel structure, a second upper channel structure overlapping with the second lower channel structure, and a second upper source/drain pattern connected to the second upper channel structure.

What exactly they claim (claim 1)

1. A semiconductor package comprising: a first logic chip; and a second logic chip overlapping with the first logic chip, wherein the first logic chip comprises: a first lower channel structure; a first lower source/drain pattern connected to the first lower channel structure; a first upper channel structure overlapping with the first lower channel structure; and a first upper source/drain pattern connected to the first upper channel structure, and wherein the second logic chip comprises: a second lower channel structure; a second lower source/drain pattern connected to the second lower channel structure; a second upper channel structure overlapping with the second lower channel structure; and a second upper source/drain pattern connected to the second upper channel structure.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
SEMICONDUCTOR PACKAGE
Publication number
US20260282531A1
Application number
19371164
Filed
Oct 28, 2025
Published
Sep 17, 2026
Inventors
1
Claims
20

Classified under

H10D 84/832 Electricity & electronicsH10D 64/254 Electricity & electronicsH10D 80/30 Electricity & electronicsH10W 20/20 Electricity & electronicsH10W 20/435 Electricity & electronicsH10W 90/00 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.