Samsung patents stacked transistor design with internal gate control
Samsung describes a semiconductor structure where two transistor layers are stacked vertically with a shared gate electrode. The design uses specific insulating spacers inside the gap between the layers to manage electrical connections and prevent interference. This approach aims to improve the efficiency of high-density memory chips.
In the filing’s own words
A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern comprising first and second semiconductor patterns, a source/drain pattern connected to the first and second semiconductor patterns, a gate electrode on the first and second semiconductor patterns, and a gate dielectric layer between the gate electrode and the first and second semiconductor patterns. An inner region is defined between a top surface of the first semiconductor pattern and a bottom surface of the second semiconductor pattern. The gate dielectric layer comprises an inner spacer in the inner region, the gate electrode comprises an inner electrode in the inner spacer, and the inner spacer comprises a first part, a second part between the inner electrode and the source/drain pattern, and a third part connecting the first part to the second part.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern comprising a first semiconductor pattern and a second semiconductor pattern vertically spaced apart from each other; a source/drain pattern connected to the first and second semiconductor patterns; a gate electrode on the first and second semiconductor patterns; and a gate dielectric layer between the gate electrode and the first semiconductor pattern and between the gate electrode and the second semiconductor pattern, wherein an inner region is defined by a first recess region formed in a top surface of the first semiconductor pattern and a second recess region formed in a bottom surface of the second semiconductor pattern, wherein the gate dielectric layer comprises an inner spacer in the inner region, wherein the gate electrode comprises an inner electrode in the inner spacer, and wherein the inner spacer comprises: a first part between the inner electrode and the second semiconductor pattern and disposed in the second recess region; a second part between the inner electrode and the source/drain pattern; and a third part connecting the first part and the second part to each other.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING GATE ELECTRODE ON TWO SPACED APART SEMICONDUCTOR PATTERNS
- Publication number
- US20260282483A1
- Application number
- 19669560
- Filed
- May 6, 2026
- Published
- Sep 17, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10D 64/018 Electricity & electronicsH10D 62/151 Electricity & electronicsH10D 64/679 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.