Samsung patents stacked capacitor design for memory chips

1. A semiconductor device, comprising: active patterns disposed on a substrate; gate structures spaced apart from each other in a second direction that is substantially parallel to an upper surface of the substrate, each of the gate structures extending in upper portions of the active patterns in a first direction that is substantially parallel to the upper surface of the substrate and substantially perpendicular to the second direction; bit line structures spaced apart from each other in the first direction, each of the bit line structures extending in the second direction on central portions of corresponding ones of the active patterns; contact plug structures disposed on opposite end portions of the active patterns; and capacitors disposed on the contact plug structures, respectively, wherein: the contact plug structures include first contact plugs and second contact plugs, the capacitors include a first capacitor and a second capacitor, the first capacitor includes: first lower electrodes spaced apart from each other on a corresponding one of the first contact plugs in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower electrodes being electrically connected to the corresponding one of the first contact plugs; first upper electrodes disposed in a space between the first lower electrodes and further disposed in a space adjacent to one of the first lower electrodes that is disposed at a first end portion; and first dielectric structures each being disposed between one of the first lower electrodes and a corresponding one of the first upper electrodes, the second capacitor includes: second lower electrodes spaced apart from each other on a corresponding one of the second contact plugs in the horizontal direction, the second lower electrodes being electrically connected to the corresponding one of the second contact plugs; second upper electrodes disposed in a space between the second lower electrodes and further disposed in a space adjacent to one of the second lower electrodes that is disposed at a first end portion; and second dielectric structures each being disposed between one of the second lower electrodes and a corresponding one of the second upper electrodes, wherein a first upper conductive pattern is disposed on and is electrically connected to the first upper electrodes, and a second conductive pattern is disposed on and is electrically connected to the second upper electrodes, and wherein the first and second conductive patterns are electrically insulated from each other.