Samsung patents memory chip design that stacks circuits between layers
Samsung describes a semiconductor device where memory cells are split into upper and lower sections. An intermediate layer sits between them, containing control circuits that connect the two memory sections using specific bonding materials.
In the filing’s own words
A semiconductor device is provided. The semiconductor device includes a lower structure including lower word lines, lower local bit lines, and lower memory cells connected to the lower word lines and the lower local bit lines; an upper structure including upper word lines, upper local bit lines, and upper memory cells connected to the upper word lines and the upper local bit lines; and an intermediate structure disposed between the lower structure and the upper structure. The intermediate structure includes word line select circuits electrically connected to the lower word lines and the upper word lines; and sub-word line drivers electrically connected to the word line select circuits.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a lower structure including a lower bonding layer; an intermediate structure disposed on the lower structure and including a first intermediate bonding layer bonded to the lower bonding layer and a second intermediate bonding layer opposing the first intermediate bonding layer; and an upper structure disposed on the intermediate structure and including an upper bonding layer bonded to the second intermediate bonding layer, wherein the lower structure further includes lower memory cells, wherein the intermediate structure further includes first peripheral circuits, wherein the upper structure further includes upper memory cells, wherein each of the lower bonding layer and the first intermediate bonding layer includes a dielectric material and does not include a bonding metal material, wherein each of the second intermediate bonding layer and the upper bonding layer includes a bonding dielectric layer including a dielectric material and bonding metal patterns including a bonding metal material, wherein the bonding dielectric layer of the second intermediate bonding layer is bonded to the bonding dielectric layer of the upper bonding layer, and wherein the bonding metal patterns of the second intermediate bonding layer are bonded to the bonding metal patterns of the upper bonding layer.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING MEMORY CELLS AND PERIPHERAL CIRCUITS
- Publication number
- US20260282395A1
- Application number
- 19566939
- Filed
- Mar 13, 2026
- Published
- Sep 17, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10B 80/00 Electricity & electronicsG11C 11/4085 Physics & computingG11C 11/4091 Physics & computingH10B 12/30 Electricity & electronicsH10B 12/50 Electricity & electronicsH10W 80/312 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.