Samsung patents chip stacking method using dummy pads for alignment
This filing describes a method for bonding two semiconductor wafers together to create a 3D chip package. It uses specific "dummy pads" placed in the empty spaces between chips to help align and bond the wafers securely.
In the filing’s own words
A method of fabricating semiconductor package device includes: preparing a first wafer and a second wafer; positioning the second wafer on the first wafer; and bonding the first wafer and the second wafer, the first wafer including: a first substrate having a first surface and a second surface; a first insulating structure; electrode layers and inter-electrode insulating layers on the first wafer,; vertical semiconductor patterns; first metal pads disposed on a top of the first insulating structure; and first dummy pads disposed on a top of the first insulating structure, the second wafer including: a second substrate having a third surface and a fourth surface; a second insulating structure; second metal pads disposed on a top of the second insulating structure; and second dummy pads disposed on a top of the second insulating structure.
What exactly they claim (claim 1)
1. A method of fabricating semiconductor package device, comprising: preparing a first wafer and a second wafer, each of the first wafer and the second wafer includes a device region and a scribe lane region; positioning the second wafer on the first wafer so that the device region of the second wafer overlaps the device region of the first wafer; and bonding the first wafer and the second wafer, wherein the first wafer includes: a first substrate having a first surface and a second surface facing the first surface; a first insulating structure on the first surface of the first substrate; electrode layers and inter-electrode insulating layers on the device region of the first wafer, the electrode layers and the inter-electrode insulating layers being alternately stacked between the first surface of the first substrate and the first insulating structure; vertical semiconductor patterns adjacent to the first substrate through the inter-electrode insulating layers and the electrode layers; first metal pads disposed on a top of the first insulating structure on the device region of the first wafer; and first dummy pads disposed on a top of the first insulating structure on the scribe lane region of the first wafer, wherein the second wafer includes: a second substrate having a third surface and a fourth surface facing the third surface; a second insulating structure on the third surface of the second substrate; second metal pads disposed on a top of the second insulating structure on the device region of the second wafer; and second dummy pads disposed on a top of the second insulating structure on the scribe lane region of the second wafer, wherein positioning the second wafer on the first wafer includes arranging the third surface of the second wafer to face the first surface of the first wafer, wherein bonding the first wafer and the second wafer includes: bonding the first metal pads and the second metal pads; and bonding the first dummy pads and the second dummy pads.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICE INCLUDING DUMMY PAD
- Publication number
- US20260282393A1
- Application number
- 19556938
- Filed
- Mar 4, 2026
- Published
- Sep 17, 2026
- Inventors
- 3
- Claims
- 20
Classified under
H10B 80/00 Electricity & electronicsH10P 54/00 Electricity & electronicsH10P 74/203 Electricity & electronicsH10P 74/273 Electricity & electronicsH10W 42/00 Electricity & electronicsH10W 42/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.