Samsung patents 3D memory using ferroelectric layers
Samsung describes a method for building a 3D memory chip by stacking layers of gate electrodes and ferroelectric material. The process involves creating holes and recesses in a stack of insulating and sacrificial layers, then filling them with electrodes and ferroelectric material to form the memory cells.
In the filing’s own words
Provided is a 3D ferroelectric memory device. The 3D ferroelectric memory device may include a plurality of gate electrodes stacked on a substrate in a first direction; a plurality of ferroelectric layers on the plurality of gate electrodes in a second direction; a plurality of intermediate electrodes on the plurality of ferroelectric layers in the second direction; a first insulating layer between the plurality of gate electrodes and between the plurality of intermediate electrodes; a second insulating layer on the plurality of intermediate electrodes and the first insulating layer; and a channel layer on the second insulating layer.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, the method comprising: alternately stacking a plurality of first insulating layers and a plurality of sacrificial layers on a substrate; forming a channel hole through the plurality of first insulating layers and the plurality of sacrificial layers; forming a plurality of first recesses by etching the plurality of sacrificial layers exposed through the channel hole to a given depth; forming a plurality of second recesses by etching portions of the plurality of first insulating layers exposed through the plurality of first recesses; forming a plurality of intermediate electrodes to fill the plurality of second recesses; depositing a second insulating layer and a channel layer on an inner wall of the channel hole; removing the plurality of sacrificial layers; depositing a plurality of ferroelectric layers on inner walls of spaces from which the plurality of sacrificial layers are removed; and forming a plurality of gate electrodes inside the plurality of ferroelectric layers.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- 3D FERROELECTRIC MEMORY DEVICE
- Publication number
- US20260282383A1
- Application number
- 19673242
- Filed
- May 11, 2026
- Published
- Sep 17, 2026
- Inventors
- 4
- Claims
- 15
Classified under
H10B 53/20 Electricity & electronicsG11C 11/223 Physics & computingH10B 51/20 Electricity & electronicsH10B 51/30 Electricity & electronicsH10B 53/30 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.