Samsung patents 3D memory layout with offset gate connections
Samsung describes a semiconductor design where two vertical stacks of memory cells sit side-by-side on a base. The filing details how electrical wires connect to the control gates of these stacks, with the connections positioned at different heights to manage the layout.
In the filing’s own words
A semiconductor device comprises a substrate; first and second stacks on the substrate, spaced apart from each other in a first direction parallel to a top surface of the substrate, and including a gate electrode extending in a second direction perpendicular to the top surface of the substrate; first and second conductive lines extending in the first direction and spaced apart from each other in a third direction perpendicular to the first direction and parallel to the top surface of the substrate; first and second gate contacts between the gate electrode of the first and second stacks, respectively, and the first and second conductive lines, respectively; wherein each of the first and second conductive lines is overlapped with the gate electrode of the first and second stacks, respectively, in the second direction, wherein each of the first and second stacks comprises channel patterns and a data storage layer.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate; a first stack and a second stack disposed on the substrate, spaced apart from each other in a first direction parallel to a top surface of the substrate, and each including a gate electrode extending in a second direction perpendicular to the top surface of the substrate; a first conductive line and a second conductive line extending in the first direction and spaced apart from each other in a third direction perpendicular to the first direction and parallel to the top surface of the substrate; a first gate contact between the gate electrode of the first stack and the first conductive line; and a second gate contact between the gate electrode of the second stack and the second conductive line, wherein each of the first conductive line and the second conductive line is overlapped with the gate electrode of the first stack and the gate electrode of the second stack in the second direction, wherein each of the first stack and the second stack comprises: channel patterns enclosing a side surface of the gate electrode and spaced apart from each other in the second direction; and a data storage layer interposed between each of the channel patterns and the gate electrode, and wherein the first gate contact and the second gate contact are offset from each other in the third direction.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- SEMICONDUCTOR DEVICES
- Publication number
- US20260282375A1
- Application number
- 19679569
- Filed
- May 15, 2026
- Published
- Sep 17, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10B 51/20 Electricity & electronicsH10B 51/10 Electricity & electronicsH10D 30/701 Electricity & electronicsH10D 64/033 Electricity & electronicsH10D 64/689 Electricity & electronicsH10W 20/435 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.