Samsung patents method for making 3D memory chips with stepped pads
Samsung has filed a patent for a specific way to build 3D semiconductor devices, likely for memory chips. The process involves creating a stack of layers, removing temporary materials to make gaps, and filling them with insulating material to create a stepped connection point.
In the filing’s own words
A method of manufacturing a semiconductor device is provided. A laminated stack of alternately stacked mold sacrificial layers and single crystal semiconductor layers is formed on an interface area of a substrate having a cell array area. First holes are formed through a cover insulating layer, and the mold sacrificial layers are removed to create first gaps. A first liner surrounds the single crystal semiconductor layers, and a second liner fills the first gaps. A gap fill insulating layer is formed, second holes are opened, and portions of the liners and single crystal semiconductor layers facing the holes are removed. A pad layer is formed at the removal location, and the second holes are filled with insulating material. The pad layer has a step-like structure parallel to the substrate surface, a constant width in a perpendicular direction, and is connected to a word line in the cell array area.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, the method comprising: forming a laminated stack including a plurality of alternately stacked mold sacrificial layers and single crystal semiconductor layers, on an interface area of a substrate comprising a cell array area and the interface area disposed on at least one side of the cell array area; forming a cover insulating layer covering the laminated stack, and then removing a portion of the cover insulating layer, to form a plurality of first holes; forming a plurality of first gaps between the plurality of single crystal semiconductor layers by removing the plurality of mold sacrificial layers through the plurality of first holes, and forming a first liner surrounding the plurality of single crystal semiconductor layers; forming a second liner on the first liner, to fill the first gaps; forming a gap fill insulating layer surrounding the plurality of first holes and the laminated stack, and removing a portion of the gap fill insulating layer to form a plurality of second holes; removing portions of the single crystal semiconductor layers, the portions facing side walls of the plurality of second holes; forming a pad layer at a location from which the single crystal semiconductor layers are removed; and filling the plurality of second holes with an insulating material, wherein the pad layer has a step-like structure in a first direction parallel to an upper surface of the substrate, has a constant width in a second direction intersecting the first direction, and is connected to a word line arranged in the cell array area.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
- Publication number
- US20260282320A1
- Application number
- 19366949
- Filed
- Oct 23, 2025
- Published
- Sep 17, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10B 12/05 Electricity & electronicsH10B 12/30 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.