Samsung patents memory erase method to reduce leakage
Samsung has filed a patent for a specific way to erase data in memory chips. The method involves pre-charging a control line before applying an erase voltage to help manage electrical leakage during the process.
In the filing’s own words
A memory device, includes a memory cell array having a plurality of memory blocks therein, including a target memory block, a voltage generator configured to generate an erase voltage and row line voltages provided to the target memory block upon to perform an erase operation, and control logic to control the memory cell array and the voltage generator, the erase voltage being provided to at least one of a bitline or a common source line, and a gate line of a transistor provided with the erase voltage being precharged, the transistor being a string select transistor having a current carrying terminals electrically coupled to the bitline, the erase voltage being provided to a drain of the string select transistor through the bitline, and the erase voltage provided to the drain of the string select transistor being transferred to a source of the string select transistor.
What exactly they claim (claim 1)
1. A memory device, comprising: a memory cell array having a plurality of memory blocks therein, including a target memory block; a voltage generator configured to generate an erase voltage and row line voltages, which are provided to the target memory block upon which an erase operation is to be performed; and control logic configured to control the memory cell array and the voltage generator; wherein the erase voltage is provided to at least one of a bitline or a common source line associated with the target memory block; and wherein a gate line of a transistor provided with the erase voltage is precharged before the erase voltage is provided to the at least one of the bitline or the common source line of the target memory block; wherein the transistor is a string select transistor having a current carrying terminals electrically coupled to the bitline; wherein the erase voltage is provided to a drain of the string select transistor through the bitline; and wherein the erase voltage provided to the drain of the string select transistor is transferred to a source of the string select transistor.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- MEMORY DEVICES SUPPORTING ENHANCED GATE-INDUCED DRAIN LEAKAGE (GIDL) ERASE OPERATION
- Publication number
- US20260279455A1
- Application number
- 19680867
- Filed
- May 18, 2026
- Published
- Sep 17, 2026
- Inventors
- 6
- Claims
- 1
Classified under
G11C 16/16 Physics & computingG11C 16/0483 Physics & computingG11C 16/08 Physics & computingG11C 16/14 Physics & computingG11C 16/24 Physics & computingG11C 16/30 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.