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Samsung patents 3D memory layout with alternating bitlines

Samsung describes a 3D memory chip design where vertical channels pass through layers of word lines to store data. The layout includes specific wiring, called bitlines and strapping lines, arranged in an alternating pattern to connect these vertical channels to the rest of the chip.

Why it mattersThis is a routine improvement in how memory cells are physically arranged, which helps manufacturers build denser storage chips.

In the filing’s own words

A semiconductor device includes word lines disposed on a substrate and spaced apart in a first direction perpendicular to an upper surface of the substrate, a string select line disposed on the word lines, memory strings extending in the first direction on the substrate, each memory string including a first channel extending in the first direction through the word lines, and memory cells constituted by the word lines around the first channel, bit lines electrically connected to the memory strings, and a strapping line connected to the string select.

What exactly they claim (claim 1)

1. A semiconductor device comprising: a plurality of word lines disposed on a substrate and spaced apart in a first direction perpendicular to an upper surface of the substrate; a string select line disposed on the plurality of word lines; a plurality of memory strings extending in the first direction on the substrate, wherein each memory string comprises: a first channel extending in the first direction through the plurality of word lines; a plurality of memory cells constituted by the plurality of word lines around the first channel; a second channel extending in the first direction through the string select line and not through any of the plurality of wordlines; and a string select transistor constituted by the string select line around the second channel; a plurality of bit lines electrically connected to the plurality of memory strings; and a strapping line connected to the string select line.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
SEMICONDUCTOR DEVICE WITH ALTERNATING BITLINES AND STRING SELECT LINES
Publication number
US20260279448A1
Application number
19680521
Filed
May 18, 2026
Published
Sep 17, 2026
Inventors
3
Claims
1

Classified under

G11C 16/08 Physics & computingG11C 8/12 Physics & computingG11C 16/0433 Physics & computingG11C 16/24 Physics & computingH10B 41/10 Electricity & electronicsH10B 41/35 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.