Samsung patents memory controller that fine-tunes data timing per pin
Samsung describes a method for a controller to communicate with multiple memory chips by adjusting the timing of incoming data signals. The system uses specific loops to align the start and end of each data signal with a reference clock, ensuring the controller reads the data accurately.
In the filing’s own words
Disclosed is an operation method of a controller which communicates with a plurality of memory devices. The method includes receiving a first reception signal, a second reception signal, and a data strobe signal, respectively, generating a first delay signal by performing first and second per-pin delay locked loop (ppDLL) operations on the first and second reception signals based on a rising edge of the data strobe signal, respectively, and generating first and second correction signals by performing first and second per-pin duty cycle correction (ppDCC) operations on the first and second delay signals based on a falling edge of the data strobe signal, respectively. Rising edges of the first and second correction signals are aligned with the rising edge of the data strobe signal, and first and second falling edges of the first correction signals are aligned with the falling edge of the data strobe signal.
What exactly they claim (claim 1)
1. A method of operating a controller which is configured to communicate with a plurality of memory devices, the method comprising: receiving a first reception signal, a second reception signal, and a data strobe signal through a first signal pin, a second signal pin, and a third signal pin, from a first memory device of the plurality of memory devices, respectively; performing a first per-pin delay locked loop (ppDLL) operation on the first reception signal and a second ppDLL operation on the second reception signal based on the data strobe signal to generate a first DLL code and a second DLL code, respectively; performing a first per-pin duty cycle correction (ppDCC) operation on the first reception signal and a second ppDCC on the second reception signal based on the data strobe signal to generate a first DCC code and a second DCC code, respectively, compensating first data signals received through the first signal pin from the plurality of memory devices based on the first ppDLL code and the first ppDCC code; and compensating second data signals received through the second signal pin from the plurality of memory device based on the second ppDLL code and the second ppDCC code.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- CONTROLLER CONFIGURED TO CONTROL MEMORY DEVICE, OPERATION METHOD OF CONTROLLER, AND STORAGE DEVICE INCLUDING MEMORY DEVICE AND CONTROLLER
- Publication number
- US20260279419A1
- Application number
- 19674741
- Filed
- May 12, 2026
- Published
- Sep 17, 2026
- Inventors
- 6
- Claims
- 20
Classified under
G11C 7/222 Physics & computingG11C 7/1093 Physics & computingG11C 2207/2254 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.