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Google patents early check for chip safety against static shocks

This filing describes a method for checking if a computer chip's static electricity protection works correctly during the early design phase. Instead of waiting until the chip is fully designed, engineers use a specific tool to model the internal structure of the protection circuits and check for weaknesses. This helps identify problems before the manufacturing process begins.

Why it mattersIt improves the efficiency of chip design by catching safety flaws earlier, which can save time and money in manufacturing.

In the filing’s own words

The present disclosure describes techniques and apparatuses that are directed to integrated circuit design and fabrication. Designers may, for example, apply the techniques to identify failing Electrostatic Discharge (ESD) clamps at a floor planning stage, rather than waiting for signoff. These techniques, including a new flow process, may successfully identify violations missed by traditional flow processes, and may identify such violations earlier in the overall design and fabrication process.

What exactly they claim (claim 1)

1. A method for verifying electrostatic discharge (ESD) protection in an integrated circuit design, the method comprising: receiving a layout of the integrated circuit design during an early design phase, the layout including at least one ESD protection circuit and not being required to be short-clean; configuring a grid-based extraction tool to model an internal structure of the at least one ESD protection circuit from an upper metal layer down to a lower metal layer; modeling layers of the integrated circuit design by modeling the internal structure of the at least one ESD protection circuit while excluding unrelated power grid geometries that do not impact ESD analysis; analyzing a resistance, a current density, or both of the at least one ESD protection circuit using the configured grid-based extraction tool to identify violations within the internal structure; and generating a verification report indicating whether the at least one ESD protection circuit meets a robustness threshold defined for the lower metal layer.

Facts

Company
Google (Google LLC)
Official title
Early-Stage Integrated Circuit Electrostatic Discharge Safeguarding
Publication number
US20260278231A1
Application number
19668927
Filed
May 6, 2026
Published
Sep 17, 2026
Inventors
2
Claims
20

Classified under

G06F 30/367 Physics & computingG06F 30/398 Physics & computingG06F 2111/10 Physics & computingG06F 2119/02 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.