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Microsoft patents chip test method to spot defects before cutting

Microsoft describes a method for testing computer chips while they are still on the large silicon wafer, before they are cut into individual pieces. The system sends a random pattern of data through the chip's communication paths and checks if the output matches the input to identify any manufacturing flaws.

Why it mattersThis helps manufacturers catch bad chips earlier in the production process, which can save money and time, though it is a standard improvement in chip manufacturing rather than a new consumer feature.

In the filing’s own words

The technology described herein provides a device including a wafer including a plurality of Tx macros, each of the Tx macro including a plurality of transmit lanes; a pseudorandom bit sequence (PRBS) generator configured on one of the Tx macros, the PRBS generator configured to generate a PRBS serial signal; a transmit data path to transmit the PRBS signal to one or more of a plurality of transmit lanes of a transmitter (Tx) macro; and a logic device to compare the output from the one or more of the plurality of transmit lanes to generate an error flag, wherein a positive value of the error flag indicates a manufacturing defect on the wafer.

What exactly they claim (claim 1)

1. A device, comprising: a wafer including a plurality of Tx macros, each of the Tx macro including a plurality of transmit lanes; a pseudorandom bit sequence (PRBS) generator configured on one of the Tx macros, the PRBS generator configured to generate a PRBS serial signal; a transmit data path to transmit the PRBS signal to one or more of a plurality of transmit lanes of a transmitter (Tx) macro; and a logic device to compare the output from the one or more of the plurality of transmit lanes to generate an error flag; wherein a positive value of the error flag indicates a manufacturing defect on the wafer.

Facts

Company
Microsoft (Microsoft Technology Licensing, LLC)
Official title
METHOD FOR PROVIDING DIE-TO-DIE TESTABILITY
Publication number
US20260278229A1
Application number
19076017
Filed
Mar 11, 2025
Published
Sep 17, 2026
Inventors
6
Claims
20

Classified under

G06F 30/333 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.